[4HV] Some points regarding gate-drive optimisation in switching power converters...

Firstly, let me say that in power electronics there is switching frequency and
there is switching speed.  The switching frequency is how many switching cycles
there are in every second (eg 100kHz,) and the switching speed describes how
rapidly these individual transitions take place. (eg 100ns.) The two things are
not the same, although they are related.

Regarding gate drive speed: it depends on the switching topology and the application
requirements (power level, efficiency, EMI limits etc.)  For example a soft-
switched resonant converter operating at 20kHz can be a lot more tolerant of slow
switching transitions than say a hard-switched boost converter running at 100kHz.

Power Electronics textbooks usually say "as fast as possible" for gate-drive slew
rates to minimise switching losses by making the power devices transition through
the dissipative linear region as quickly as possible.  In real life however, things
are not that simple.  Diodes need finite time to reverse-recover, and device
capacitances must be charged during the switching transitions. Rapidly diverting the
path of heavy currents across a PCB also causes Ldi/dt voltage spikes across stray
inductance, followed by ringing and serious EMI problems  -  Something familiar to
anyone who designs switched-mode power supplies for CE or FCC approvals markets.

My rule of thumb for commercial power electronics work is that gate drive should be
as fast as necessary and no faster.  In general you start with moderately fast
switching transitions and gradually increase gate resistance to slow down the
switching trajectory whilst monitoring device temperature, EMI & waveforms.  EMI will
initially fall rapidly.  Device temperature also often falls initially too because
you are giving diodes more time to reverse-recover, less ringing avalanching etc.
You reach a point where device temp is at a minimum, and beyond that point any
further increase in gate resistance causes increasing dissipation due to prolonged
V-I overlap in the devices. In general this is the point where you want to be
operating, because it gives good efficiency,  clean waveforms and good EMI
performance. So you can see that those gate resistors in SMPSUs aren't just chosen
at random!  (Such tests are normally done near full load current, minimum input
volts and max temperature but you have to be careful of not inducing thermal runaway
by slowing the gate-drive too much at full power!  Ideally they would then be checked
under various line, load and temperature conditions.)

With MOSFETs there is nothing to inherently limit how fast you can switch the device
other than how quickly you can charge or discharge all of the gate structure.
Although it is theoretically possible to latch-up a MOSFET by trying to turn-off a
huge current instantaneously it takes some effort to achieve this in practice!  In
any given application the MOSFET device is generally not the limiting factor, but
rather the voltage overshoots that occur from Ldi/dt in the rest of the circuit as
Steve C already pointed out.  (You will avalanche the device is the drain-source
capacitance doesn't snub the spike sufficiently.)

As for IGBTs and turn-off transitions in particular, it depends on the IGBT
generation and its tolerance to di/dt induced latch-up. Old IGBTs used to be
notorious for latchup when presented with the wrong combination of collector current,
die temperature and gate drive at turn-off. You should be able to get this information
from the device's commutating safe operating area (or turn-off SOA) graph.  Ideally
you don't want to be repeatedly interrupting a large current anyway because it will
cause tail current losses, but above the critical commutating current there is risk
of triggering the parasitic thyristor structure, which can then latch destroying the
device.  Thyristor gain increases with temp so this critical current falls as the
device warms up.  Many modern IGBTs are sold as "short-circuit proof." These can
clearly interrupt the rated s/c current safely within the specified time and latchup
is largely a thing of the past, but this does not apply if you over-volt the gates
to further enhance the device, or otherwise depart from the test conditions on the
datasheet!
 
Discontinuous flyback type power supplies would be most at risk here because the
device current is at a peak of many times the average current right before the device
is asked to switch off.  Latch up in a DRSSTC though?  Not likely unless you tell an
IGBT to switch off mid-way through a half-cycle of the load current.  (The popular
HGT1N40N60A4D device is specified to have a critical turn-off current of 200A under
the test conditions specified its the datasheet.)  Under normal operation the load
current has passed through zero and moved into the free-wheel diode some time before
the IGBT has been told to "switch off."  

Perhaps a good excercise in where switching speeds matter and don't matter is in the
DRSSTC.  IGBT's switch after the sinusoidal load current has been detected to have
passed through zero.  By this time the load current has already commutated to the free-
wheel diode so the speed at which the IGBT turn's off *initially* appears irrelevant?
However, it is important that the other IGBT should start to turn on as soon as
possible after the current zero in order to recover the load current that is building
in the free-wheel diode as quickly as possible.  Although this IGBT should start to
turn on soon it must not do so until the opposing device is able to block applied
voltage, and when it does turn on it should do so with a controlled profile.  The
reason is that it only has to support the relatively slowly growing sinusoidal load
current as it rises up from zero.  Turning the device on suddenly just results in
a surge of current to shock charge the oppposite device's output capacitance, and
forced reverse-recovery of the opposing free-wheel diode as the full DC bus voltage
is slammed across an already conducting diode.  This is accompanied by the trademark
surge of current from the DC bus that puts ringing on every signal within 3 feet and
blanks out radio reception!  You only need to turn on the device at a rate that
ensures it is sufficiently enhanced to carry the instantaneous load current that flows
at that point in time.  Anything faster just exacerbates the problems explained above.

A similar situation happens with Class E amplifiers. At turn-on the MOSFET sees zero
voltage and zero current, so there is some leeway in when the device is turned on
and how quickly.  Once the device has started to turn-on the resonant load current also
builds in a sinusoidal way, so the device only needs to be sufficiently enhanced
to support this load current as it grows.  That is why sinusoidal gate drive is able to
work for Class E power stages running tens of MHz without huge switching losses.  At
the turn-on transition it is almost the perfect waveshape!  At the turn-off transition
we would like to turn the device off as quickly as possible.  In practice the drain-
source capacitance controls the rate at which drain voltage rises, so there still
isn't much overlap of V and I even if the turn-off speed is also quite slow.

Something worth noting is that adding resistance to the gate circuit of a MOSFET
or IGBT to slow down the turn-off also reduces its immunity to dv/dt induced turn-on.
Basically when the drain voltage of a MOSFET rises very quickly a current flows
into the drain to charge the capacitances of the device.  A portion of this current
actually flows through the "Miller" Cdg capacitance and appears at the gate.  If the
gate is not actively pulled low it can rise above the gate-source threshold voltage and
the device begins to conduct.  This is known as dv/dt induced turn-on.  The best ways
to combat this are to pull the gate negative with respect to the source when you want
the device to be turned off, and to do this through a low impedance.  The low impedance
means that most of the miller current is sinked by the driver, and the negative bias
improves the turn-on margin because the gate voltage starts from say -10 instead of 0
volts.  (IGBTs also exhibit the same effect, although it is usually reduced. This is
beacuase similarly rated IGBTs are usually one or two die sizes smaller than the
equivalent MOSFETs so device capacitances are smaller.)  If you are interested read
up about gate drives....  The miller plataeu region on the gate drive waveform
actually gives you some indictaion how long your MOSFETs take to switch.

An additional point regarding gate-drive chip's massive output current capabilities...
A high output current sourcing and sinking ability is only useful if you are *directly*
connecting the driver chip to the device's gates. Once there is any length of wire or
leakage inductance from a ferrite gate-drive transformer between the driver IC and the
gate capacitance, this peak current is rarely reached anyway.  If you don't beleive me
then work out the surge impedance, or calculate how small a stray inductance value you
would need to reach the 10A limit of your driver chip within 50ns.  In practice you
don't even do as well as the surge impedance would suggest because some resistance must
then be added to reduce ringing to an acceptable level.  (The fastest gate drive is
always obtained by direct connection to the switching device right at its terminals,
GDT's trade some of this switching speed for the convenience of remote drive and
electrical isolation.)

An excellent paper to read that covers a lot of what I said here is APT0101 from
Advanced Power Technology. Even if you don't need or want to know what a PFC is, the
section about gate-drive optimisation and the waveforms are definitely worth a look.

http://www.microsemi.com/micnotes/APT0101.pdf

-Richie,